1. Field of the Invention
The present invention relates to solid state charge coupled device image sensors and more particularly to apparatus for compensating for column defects in such image sensors.
2. Description of the Problem
The use of solid state charge coupled device (CCD) area array image sensors is well known in the art. Several readout organizations for such CCD area array image sensors are known, including line addressed, frame transfer, and interline transfer-type devices. See for example, "Charge Transfer Devices" by Sequin and Tompsett, Academic Press Inc., 1975, page 153. These readout organizations share the feature that rows (or columns) of charge packets are shifted in parallel into a CCD output register from which they are read out serially. For example, in the frame transfer type device, an imagewise pattern of photocharges is accumulated in a two-dimensional array of image sensing elements. The photocharges are then quickly shifted to a two-dimensional storage array. Rows of photocharge are shifted in parallel from the storage array into an output register, and the rows are read out serially.
Although it is a goal to manufacture such image sensors free from defects, this goal is difficult to achieve in practice. Several forms of defects arising in the manufacturing process, such as intralevel shorts between the electrodes, small breaks or partially missing electrodes, an extension of the channel stopping dopants into a channel, or a pinhole in the gate oxide acting as a sink for minority characters cause entire columns of photocharge to be so noisy as to be unusable. The affect of the noise appears as a vertical bar in the image reproduced from the signal. Since the yield of perfect devices without column defects is relatively low, but the yield of devices with only a few bad columns is relatively high, there is a large incentive to compensate for the bad columns in the output of such devices so that less than perfect sensors may be used.
Previous approaches to defect compensation have been directed toward individual elements, for example, see U.S. Pat. No. 4,167,754 issued to Nagumo et al, Sept. 11, 1979, which describes the use of a separate programable read/only memory (PROM) containing the coded location of each defective element in a CCD area array. The PROM is addressed while the image sensor is operated and readout of the sensor is effected by enabling a sampling and hold circuit at the output of the array only when a signal from a nondefective element is produced. This method has the effect of replacing the signal from the defective element with the signal from an adjacent nondefective element. Although the coding scheme employed by Nagumo et al significantly reduces the size of the required PROM, the electronics used to address the PROM and decode the information stored therein, still adds significantly to the cost of the defect compensation circuit. In addition, for column defects, the disclosed scheme would contain one correction code word for each element in a defective column, e.g. 500 correction words if the sensor had 500 rows of sensor elements. Another approach to defect compensation disclosed in U.S. Pat. No. 4,179,711 to Nagumo, issued Dec. 18, 1979, employs a duplicate solid state image sensor over which is disposed a mask having a pattern representative of the location of the defective sensor elements. The duplicate image sensor is uniformly exposed with light and is read out in synchronism with the main sensor. The signals produced by the duplicate image sensor are employed to gate a sample and hold circuit as described above to replace the signals from defective elements with signals from adjacent nondefective elements. This approach is likewise expensive since an entire extra image sensor needs to be provided.
The problem faced by the inventor therefore, was to provide a simple, inexpensive apparatus for compensating for column defects in a CCD area array image sensor.